1. Field of the Invention
The present invention relates to a liquid crystal display panel using a horizontal electric field, and more particularly, to a thin film transistor array substrate of such a liquid crystal display panel and a fabricating method thereof.
2. Description of the Related Art
Generally, liquid crystal displays (LCD's) control light transmittance of liquid crystal using an electric field, thereby displaying a picture. Liquid crystal displays are largely classified into a vertical electric field type and a horizontal electric field type depending upon the direction of the electric field driving the liquid crystal. The liquid crystal display of vertical electric field applying type drives a liquid crystal in a twisted nematic (TN) mode with a vertical electric field formed between a pixel electrode and a common electrode arranged in opposition to each other on the upper and lower substrate. The liquid crystal display of vertical electric field type has an advantage of a large aperture ratio while having a drawback of a narrow viewing angle of about 90°. The liquid crystal display of the horizontal electric field applying type drives a liquid crystal in an in plane switch (IPS) mode with a horizontal electric field between the pixel electrode and the common electrode arranged parallel to each other on the lower substrate. The liquid crystal display of a horizontal electric field type has an advantage of a wide viewing angle (i.e., up to about 160°).
Hereinafter, the liquid crystal display of horizontal electric field type will be described in detail. The liquid crystal display of the horizontal electric field type includes a thin film transistor array substrate and a color filter array substrate joined to each other, a spacer for uniformly maintaining a cell gap between two substrates, and a liquid crystal filled into a liquid crystal space defined by the spacer. The thin film transistor array substrate comprises a plurality of signal lines for forming a horizontal electric field in each pixel, a plurality of thin film transistors, and an alignment film coated thereon to align the liquid crystal. The color filter array substrate includes a color filter for implementing a color, a black matrix for preventing a light leakage, and an alignment film coated thereon to align the liquid crystal.
FIG. 1 is a plan view showing a structure of a thin film transistor array substrate of a related art liquid crystal display of horizontal electric type, and FIG. 2 is a cross-sectional view of the thin film transistor array substrate taken along line I-I′ of FIG. 1. Referring to FIG. 1 and FIG. 2, the thin film transistor array substrate of the related art liquid crystal display of horizontal electric field type includes a gate line 2 and a data line 4, which intersect each other provided on a lower substrate 1, a thin film transistor 30 provided at each intersection, a pixel electrode 22 and a common electrode 24 provided in a pixel area defined by the intersecting gate and data lines, and a common line 26 connected to the common electrode 24. Further, the thin film transistor array substrate includes a storage capacitor 40 provided at an overlapped portion between the pixel electrode 22 and the common line 26, a gate pad 50 connected to the gate line 2, a data pad 60 connected to the data line 4 and a common pad 80 connected to the common line 26.
The thin film transistor 30 allows a pixel signal of the data line 4 to be charged and maintained on the pixel electrode 22 in response to a gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode 10 connected to the pixel electrode 22. Further, the thin film transistor 30 includes an active layer 14 overlapping the gate electrode 6 with a gate insulating film 12 therebetween to define a channel between the source electrode 8 and the drain electrode 10. The active layer 14 also overlaps the data line 4, a lower data pad electrode 62 and a storage electrode 28. On the active layer 14, ohmic contact layer 16 for making an ohmic contact with the data line 4, the source electrode 8, the drain electrode 10, the lower data pad electrode 62 and the storage electrode 28 are further provided.
The pixel electrode 22 is connected via a first contact hole 32 going through a protective film 18, to the drain electrode 10 of the thin film transistor 30 and is provided in the pixel area. Particularly, the pixel electrode 22 includes a first horizontal portion 22a connected to the drain electrode 10 and provided parallel with adjacent gate lines 2, a second horizontal portion 22c overlapping with the common line 26, and a finger portion 22b provided in parallel to the common electrode 24 between the first and second horizontal portions 22a and 22b. The common electrode 24 is connected to the common line 26 and is provided at the pixel area. Specifically, the common electrode 24 is provided parallel to the finger portion 22b of the pixel electrode 22 in the pixel area. Accordingly, a horizontal electric field is formed between the pixel electrode 22 to which a pixel signal is supplied via the thin film transistor 30 and the common electrode 24 to which a reference voltage is supplied via the common line 26. More specially, the horizontal electric field is formed between the finger portion 22b of the pixel electrode 22 and the common electrode 24. Liquid crystal molecules arranged in the horizontal direction between the thin film transistor array substrate and the color filter array substrate by such a horizontal electric field are rotated due to a dielectric anisotropy. Transmittance of a light transmitting the pixel area is differentiated depending upon a rotation extent of the liquid crystal molecules, thereby implementing a gray level scale.
The storage capacitor 40 consists of the gate line 2, the storage electrode 28 overlapping the gate line 2 having the gate insulating film 12, the active layer 14 and the ohmic contact layer 16 therebetween, and the pixel electrode 22 connected, via a second contact hole 34 going through the protective film 18, to the storage electrode 28. The storage capacitor 40 allows a pixel signal charged on the pixel electrode 22 to be stably maintained until the next pixel signal is charged. The gate line 2 is connected, via the gate pad 50, to a gate driver (not shown). The gate pad 50 consists of a lower gate pad electrode 52 extended from the gate line 2, and an upper gate pad electrode 58 connected, via a third contact hole 54 going through the gate insulating film 12 and the protective film 18, to the lower gate pad electrode 52. The data line 4 is connected, via the data pad 60, to the data driver (not shown). The data pad 60 consists of a lower data pad electrode 62 extended from the data line 4, and an upper data pad electrode 68 connected, via a fourth contact hole 64 going through the protective film 18, to the lower data pad electrode 62. The common line 26 receives a reference voltage from an external reference voltage source (not shown) through the common pad 80. The common pad 80 consists of a lower common pad electrode 82 extended from the common line 86, and an upper common pad electrode 88 connected, via a fifth contact hole 84 going through the gate insulating film 12 and the protective film 18, to the lower common pad electrode 82.
A method of fabricating the thin film transistor array substrate having the above-mentioned structure will be described in detail with reference to FIGS. 3A to 3J. First, as shown in FIG. 3A, a gate metal layer 5 is formed on the lower substrate 1 by a deposition technique, such as sputtering. Then, a photo-resist pattern 72 is formed by photolithography, including exposure and development processes using a first mask 70 defining a shielding area S2 and an exposure area S1. The gate metal layer 5 is patterned by an etching process using the photo-resist pattern 72, thereby providing a first conductive pattern group including the gate line 2, the gate electrode 6, the lower gate pad electrode 52, the common line 26, the common electrode 24 and the lower common pad electrode 82 on the lower substrate 1 as shown in FIG. 3B.
As shown in FIG. 3C, the gate insulating film 12, an amorphous silicon layer 13 and an n+ amorphous silicon layer 15 are sequentially formed on the lower substrate 1 by a deposition technique, such as PECVD or sputtering, etc. Then, a photo-resist pattern 76 is formed by the photolithography including exposure and development process using a second mask 74 defining a shielding area S2 and an exposure area S1. The amorphous silicon layer 13 and the n+ amorphous silicon layer 15 are patterned by an etching process using the photo-resist pattern 76, thereby providing a semiconductor pattern including the active layer 14 and the ohmic contact layer 16 on the lower substrate 1, as shown in FIG. 3D.
As shown in FIG. 3E, a data metal layer 9 is formed on the gate insulating film 12 provided with the semiconductor pattern by a deposition technique, such as sputtering, etc. Then, a photo-resist pattern 90 is formed by photolithography including exposure and development process using a third mask 78 defining a shielding area S2 and an exposure area S1. The data metal layer 9 is patterned by the etching process using the photo-resist pattern 90, thereby providing a second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, the storage electrode 28 and the lower data pad electrode 62 on the lower substrate 1, as shown in FIG. 3F. Subsequently, the exposed ohmic contact layer 16 between the source electrode 8 and the drain electrode 10 are etched by utilizing the source electrode 8 and the drain electrode 10 as a mask. Thus, the active layer 14 at the channel portion of the thin film transistor 30 is exposed.
As shown in FIG. 3G, the protective film 18 is entirely formed on the gate insulating film 12 provided with the second conductive pattern by a deposition technique such as PECVD, etc. Then, a photo-resist pattern 94 is formed by the photolithography including exposure and development process using a fourth mask 2 defining a shielding area S2 and an exposure area S1. The protective film 18 is patterned by an etching process using the photo-resist pattern 94, thereby providing the first to fifth contact holes 32, 34, 54, 64 and 84 as shown in FIG. 3H. As shown in FIG. 3I, a transparent conductive film 21 is coated onto the protective film 18 having the first to fifth contact holes 32, 34, 54, 64 and 84 by a deposition technique such as the sputtering, etc. Then, a photo-resist pattern 98 is formed by photolithography including exposure and development process using a fifth mask 96 defining a shielding area S2 and an exposure area S1. The transparent conductive film 21 is patterned by an etching process using the photo-resist pattern 98 to thereby provide a third conductive pattern group including the pixel electrode 22, the upper gate pad electrode 58, the upper data pad electrode 68 and the upper common pad electrode 88, as shown in FIG. 3J.
As described above, in the related art thin film transistor array substrate and a fabricating method thereof, the photolithography process is a series of processes including photo-resist coating, mask alignment, light-exposure, development and stripping, etc. Such photolithography process has the problems of a long process requirement time, a large waste of a stripper liquid for removing the photo-resist and the photo-resist pattern and expensive equipment such as an exposure device, etc. Particularly, as a dimension of the substrate is made larger and a size of the pattern becomes smaller, the cost of the exposure device increases.